View CS5460A-KS_277944.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS5460A
Single Phase Bi-Directional Power/Energy IC
Features
l Energy Data Linearity: 0.1% of Reading over
Description
The CS5460A is a highly integrated Analog-to-Digital Converter (ADC) which combines two ADCs, high speed power calculation functions, and a serial interface on a single chip. It is designed to accurately measure and calculate: Energy, Instantaneous Power, IRMS, and VRMS for single phase 2- or 3-wire power metering applications. The CS5460A interfaces to a low cost shunt or transformer to measure current, and resistive divider or transformer to measure voltage. The CS5460A features a bi-directional serial interface for communication with a micro-controller and a programmable frequency output that is proportional to energy. CS5460A has on-chip functionality to facilitate AC or DC system-level calibration. The "Auto-Boot" feature allows the CS5460A to function "stand-alone" and to initialize itself on system power up. In Auto-Boot Mode, the CS5460A reads the calibration data and start-up instructions from an external EEPROM. In this mode, the CS5460A can work without the need for a microprocessor, for low-cost metering applications.
1000:1 Dynamic Range l On-Chip Functions: Energy, I V, IRMS and VRMS, Energy to Pulse-Rate Conversion l Smart "Auto-Boot" Mode from Serial EEPROM with no microcontroller. l AC or DC System Calibration l Mechanical Counter/Stepper Motor Driver l Meets Accuracy Spec for IEC 687/1036, JIS l Power Consumption <12 mW l Interface Optimized for Shunt Sensor l Phase Compensation l Ground-Referenced Signals with Single Supply l On-chip 2.5 V Reference (MAX 60 ppm/C drift) l Simple Three-Wire Serial Interface l Watch Dog Timer l Power Supply Monitor l Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V
VA+
ORDERING INFORMATION: CS5460A-BS -40C to +85C CS5460A-KS 0C to +70C
RESET High Pass Filter VD+ Watch Dog Timer MODE Power Calculation Engine (Energy I*V I RMS ,V RMS ) Digital Filter High Pass Filter E-to-F CS SDI Serial Interface SDO SCLK INT EDIR EOUT
24-pin SSOP 24-pin SOIC
IIN+ IIN-
PGA x10,x50 Modulator 4 th Order Digital Filter
VIN+ VIN-
x10
2 nd Order Modulator
VREFIN
x1
VREFOUT
Voltage Reference
Power Monitor
System Clock
/K
Clock Generator
Calibration SRAM
VA-
PFMON
XIN
XOUT CPUCLK
DGND
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
JUL `00 DS284PP2 1
CS5460A
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 5 ANALOG CHARACTERISTICS ............................................................................................... 5 5 V DIGITAL CHARACTERISTICS .......................................................................................... 7 3 V DIGITAL CHARACTERISTICS .......................................................................................... 8 ABSOLUTE MAXIMUM RATINGS .......................................................................................... 8 SWITCHING CHARACTERISTICS ......................................................................................... 9 2. GENERAL DESCRIPTION ...................................................................................................... 12 2.1 Theory of Operation ......................................................................................................... 12 2.2 Performing Measurements............................................................................................... 13 2.2.1 Single Computation Cycle (C = 0) .......................................................................... 14 2.2.2 Multiple Computation Cycles (C = 1)...................................................................... 14 2.3 High Rate Digital Filters ................................................................................................... 15 2.4 High-Pass Filters.............................................................................................................. 15 3. SERIAL PORT OVERVIEW..................................................................................................... 15 3.1 Commands (Write Only) .................................................................................................. 16 3.1.1 Start Conversions................................................................................................... 16 3.1.2 SYNC0 Command.................................................................................................. 16 3.1.3 SYNC1 Command.................................................................................................. 16 3.1.4 Power-Up/Halt ........................................................................................................ 16 3.1.5 Power-Down........................................................................................................... 17 3.1.6 Calibration .............................................................................................................. 17 3.1.7 Register Read/Write ............................................................................................... 18 3.2 Serial Port Interface Pins ................................................................................................. 19 3.3 Serial Read and Write...................................................................................................... 19 3.3.1 Register Write......................................................................................................... 19 3.3.2 Register Read ........................................................................................................ 19 3.4 Serial Port Initialization .................................................................................................... 21 3.5 System Initialization ......................................................................................................... 21 4. FUNCTIONAL DESCRIPTION ................................................................................................ 22 4.1 Pulse-Rate Output ........................................................................................................... 22 4.2 Multi-Phase Option for Pulse Output ............................................................................... 23 4.3 Pulse Output for Normal Mode, Stepper Motor Mode and Mechanical Counter Mode................................................................................................................... 25 4.3.1 Normal Mode.......................................................................................................... 25 4.3.2 Mechanical Counter Mode ..................................................................................... 25 4.3.3 Stepper Motor Mode............................................................................................... 25
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Microwire is a trademark of National Semiconductor Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS284PP2
CS5460A
4.4 Auto-Boot Mode Using EEPROM.................................................................................... 25 4.5 Interrupt and Watchdog Timer ......................................................................................... 28 4.5.1 Interrupt.................................................................................................................. 28 4.5.1.1 Clearing the Status Register......................................................................... 28 4.5.1.2 Typical use of the INT pin ............................................................................. 28 4.5.1.3 INT Active State............................................................................................ 28 4.5.1.4 Exceptions .................................................................................................... 28 4.5.2 Watch Dog Timer ................................................................................................... 28 4.6 Oscillator Characteristics ................................................................................................. 29 4.7 Analog Inputs................................................................................................................... 29 4.8 Voltage Reference ........................................................................................................... 29 4.9 Calibration ....................................................................................................................... 29 4.9.1 Overview of Calibration Process ............................................................................ 29 4.9.2 The Calibration Registers....................................................................................... 30 4.9.3 Calibration Sequence............................................................................................. 30 4.9.4 Duration of Calibration Sequence .......................................................................... 31 4.9.5 Description of Calibration Algorithms ..................................................................... 31 4.9.6 Is Calibration Required?......................................................................................... 32 4.9.7 Calibration Tips ...................................................................................................... 33 4.10 Phase Compensation .................................................................................................... 33 4.11 Time-Base Calibration Register..................................................................................... 33 4.12 Power Offset Register ................................................................................................... 34 4.13 Input Protection and Filtering......................................................................................... 34 4.14 PCB Layout ................................................................................................................... 35 5. REGISTER DESCRIPTION ..................................................................................................... 36 5.1 Configuration Register ..................................................................................................... 36 5.2 DC Current Offset Register and DC Voltage Offset Register .......................................... 38 5.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register .................................. 38 5.4 Cycle Count Register....................................................................................................... 38 5.5 Pulse-Rate Register ........................................................................................................ 39 5.6 I,V,P,E Signed Output Register Results .......................................................................... 39 5.7 IRMS, VRMS Unsigned Output Register Results ............................................................ 39 5.8 Timebase Calibration Register ........................................................................................ 39 5.9 Power Offset Register ..................................................................................................... 40 5.10 AC Current Offset Register and AC Voltage Offset Register ........................................ 40 5.11 Status Register and Mask Register ............................................................................... 40 5.12 Control Register............................................................................................................. 42 6. PIN DESCRIPTION.................................................................................................................. 43 7. PACKAGE DIMENSIONS ....................................................................................................... 45
DS284PP2
3
CS5460A
LIST OF FIGURES
Figure 1. SDI Write Timing (Not to Scale) ..................................................................................... 10 Figure 2. SDO Read Timing (Not to Scale) ................................................................................... 10 Figure 3. CS5460A Auto-Boot Sequence Timing.......................................................................... 11 Figure 4. Typical Connection Diagram (One-Phase 2-Wire)......................................................... 12 Figure 5. Typical Connection Diagram (One-Phase 3-Wire)......................................................... 13 Figure 6. Data Flow ....................................................................................................................... 14 Figure 7. Voltage Input Filter Characteristics ................................................................................ 15 Figure 8. Current Input Filter Characteristics ................................................................................ 15 Figure 9. Command and Data Word Timing.................................................................................. 20 Figure 11. Option for wire and configuration of EOUT and EDIR pins for multi-phase metering .. 24 Figure 10. Multi-Phase System (Normal Mode only)..................................................................... 24 Figure 12. Mechanical Counter Mode on EOUT and EDIR........................................................... 25 Figure 13. Stepper Motor Mode on EOUT and EDIR.................................................................... 25 Figure 14. Typical Interface of EEPROM to CS5460A.................................................................. 26 Figure 15. Timing Diagram for Auto-Boot Sequence .................................................................... 27 Figure 16. Oscillator Connection ................................................................................................... 29 Figure 17. System Calibration of Gain. ......................................................................................... 31 Figure 18. System Calibration of Offset. ....................................................................................... 31 Figure 19. Calibration Data Flow................................................................................................... 32 Figure 20. CS5460A Register Diagram......................................................................................... 36
LIST OF TABLES
Table 1. Output Linearity after Calibration with MCLK = 4.096 MHz, K = 1, N = 4000.................. 14 Table 2. Internal Registers Default Value...................................................................................... 21
4
DS284PP2
CS5460A
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = -40 C to +85 C; VA+, VD+ = +5 V 10%; VREFIN = 2.5 V;
VA- = AGND; MCLK = 4.096 MHz, K = 1; N = 4000, OWR = 4.0 kHz.)(See Notes 1, 2, and 3) Parameter Symbol THD CMRR Min 74 80 IIN 0 0 -0.25 IC EII 30 30 VOS FSE VIN 0 -0.25 (50, 60 Hz) IC (Note 4) EII 5 (Note 1) (Note 1) VOS FSE 0.2 20 4 0.001 0.001 250 VA+ -70 250 0.01 0.01 k k Vrms Vrms %F.S. %F.S. mV(dc) V dB pF M Vrms %F.S. %F.S. Typ 5 25 25 Max 250 50 VA+ -115 Unit dB dB nV/C mV(dc) mV(dc) V dB pF pF
Accuracy (Both Channels) Total Harmonic Distortion Common Mode Rejection (DC, 50, 60 Hz) Offset Drift (Without the High Pass Filter) Analog Inputs (Current Channel) Differential Input Voltage Range {(IIN+) - (IIN-)} (Gain = 10) (Gain = 50) Common Mode + Signal on IIN+ or IIN(Gain = 10 or 50) Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) Input Capacitance (Gain = 10) (Gain = 50) Effective Input Impedance (Note 4) (Gain = 10) (Gain = 50) Noise (Referred to Input) (Gain = 10) (Gain = 50) Accuracy (Current Channel) Bipolar Offset Error Full-Scale Error Analog Inputs (Voltage Channel) Differential Input Voltage Range
Common Mode + Signal on VIN+ or VINCrosstalk with Current Channel at Full Scale Input Capacitance Effective Input Impedance Noise (Referred to Input) (Note 1) (Note 1) {(VIN+) - (VIN-)}
Accuracy (Voltage Channel) Bipolar Offset Error Full-Scale Error
Notes: 1. Applies after system calibration
2. Specifications guaranteed by design, characterization, and/or test. 3. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted. 4. Effective Input Impedance (EII) is determined by clock frequency (DCLK) and Input Capacitance (IC). EII = 1/(IC*DCLK/4)
DS284PP2
5
CS5460A
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol Dynamic Characteristics Phase Compensation Range (Voltage Channel, 60 Hz) High Rate Filter Output Word Rate (Both Channels) OWR Input Sampling Rate DCLK = MCLK/K Full Scale DC Calibration Range (Note 5) FSCR Channel-to-Channel Phase Error (60 Hz) (when PC[6:0] bits are set to "0000000") High Pass Filter Pole Frequency -3 dB Reference Output Output Voltage REFOUT Temperature Coefficient Load Regulation (Output Current 1 A Source or Sink) VR Output Noise Voltage (0.1 Hz to 512 kHz) eN VREFIN Min -2.4 25 Typ DCLK/1024 DCLK/4 0.02 2.4 2.4 IA+ ID+ (VD+ = 5 V) ID+ (VD+ = 3 V) PSCA PSCD PSCD PC 56 70 2.3 2.7 0.5 25 6 100 2.5 4 25 1.3 2.9 1.7 21 11.6 6.75 10 PSRR PSRR PM 2.6 60 10 2.6 25 dB dB V Max +2.5 100 Unit Hz Hz %F.S. Deg Hz V ppm/C mV Vrms V pF nA mA mA mA mW mW mW W
Reference Input Input Voltage Range Input Capacitance Input CVF Current Power Supplies Power Supply Currents (Normal Mode)
Power Consumption (Note 6)
Normal Mode (VD+ = 5 V) Normal Mode (VD+ = 3 V) Standby Sleep (50, 60 Hz) (Gain = 10) (Gain = 50)
Power Supply Rejection
Power Monitor Hysteresis Thresholds
Notes: 5. The minimum FSCR is limited by the maximum allowed gain register value. 6. All outputs unloaded. All inputs CMOS level.
6
DS284PP2
CS5460A
5 V DIGITAL CHARACTERISTICS (TA =
0 V) (See Notes 2 and 7) Parameter High-Level Input Voltage All Pins Except XIN and SCLK and /RESET XIN SCLK and /RESET Low-Level Input Voltage All Pins Except XIN and SCLK and /RESET XIN SCLK and /RESET High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Iout = +5 mA Iout = -5 mA Symbol VIH 0.6 VD+ (VD+) - 0.5 0.8 VD+ VIL VOH VOL Iin IOZ Cout (VD+) - 1.0 1 5 0.8 1.5 0.2 VD+ 0.4 10 10 V V V V V A A pF V V V Min Typ Max Unit -40 C to +85 C; VA+, VD+ = 5 V 10% VA-, DGND =
DS284PP2
7
CS5460A
3 V DIGITAL CHARACTERISTICS (TA =
VA-, DGND = 0 V) (See Notes 2 and 7) Parameter High-Level Input Voltage All Pins Except XIN and SCLK and /RESET XIN SCLK and /RESET Low-Level Input Voltage All Pins Except XIN and SCLK and /RESET XIN SCLK and /RESET High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Iout = +5 mA Iout = -5 mA Symbol VIH 0.6 VD+ (VD+) - 0.5 0.8 VD+ VIL VOH VOL Iin IOZ Cout (VD+) - 1.0 1 5 0.48 0.3 0.2 VD+ 0.4 10 10 V V V V V A A pF V V V Min Typ Max Unit -40 C to +85 C; VA+ = 5 V 10%, VD+ = 3 V 10%;
Notes: 7. All measurements performed under static conditions.
ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 8)
Parameter DC Power Supplies (Notes 9 and 10) Positive Digital Positive Analog Negative Analog (Note 11 and 12) Symbol VD+ VA+ VAIIN IOUT (Note 13) All Analog Pins All Digital Pins PDN VINA VIND TA Tstg Min -0.3 -0.3 +0.3 - 0.3 -0.3 -40 -65 Typ Max +6.0 +6.0 -6.0 10 25 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 8. All voltages with respect to ground. 9. VA+ and VA- must satisfy {(VA+) - (VA-)} +6.0 V. 10. VD+ and VA- must satisfy {(VD+) - (VA-)} +6.0 V. 11. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. 12. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 13. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 8 DS284PP2
CS5460A
-40 C to +85 C; VA+ = 5.0 V 10%; VD+ = 3.0 V 10% or 5.0 V 10%; VA- = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF)) Parameter Master Clock Frequency Internal Gate Oscillator (Note 14) Master Clock Duty Cycle CPUCLK Duty Cycle (Note 15) Rise Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output Fall Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output Start-up Oscillator Start-up Time XTAL = 4.096 MHz (Note 17) Symbol MCLK Min 2.5 40 40 200 200 50 50 100 100 50 48 100 0 50 50 100 50 20 50 Typ 4.096 50 50 60 Max 20 60 60 1.0 100 1.0 100 2 150 150 150 Unit MHz % % s s ns s s ns ms MHz ns ns ns ns ns ns ns ns ns ns MCLK ns ns ns ns ns ns
SWITCHING CHARACTERISTICS (TA =
trise
tfall
tost SCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17
Serial Port Timing Serial Clock Frequency Serial Clock SDI Write Timing CS Enable to Valid Latch Clock
Data Set-up Time Prior to SCLK Rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable
Pulse Width High Pulse Width Low
SDO Read Timing CS Enable to Valid Latch Clock
SCLK Falling to New Data Bit CS Rising to SDO Hi-Z
Auto-Boot Timing MODE setup time to /RESET rising
/RESET rising to /CS falling /CS falling to SCLK rising SDO out from SCLK falling hold time SDI input to SCLK rising setup time SDI input from SCLK rising hold time SCLK falling to /CS rising /CS rising to driving MODE low (to end auto-boot sequence).
Notes: 14. Device parameters are specified with a 4.096 MHz clock, however, clocks between 3 MHz to 20 MHz can be used. 15. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec. 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.
DS284PP2
9
CS5460A
CS
SDI
MSB t3
MSB - 1 t4 t5 t1 t2
LSB t6
SCLK
Figure 1. SDI Write Timing (Not to Scale)
CS t7 SDO MSB t8 SCLK MSB - 1 t1 t2 LSB t9
Figure 2. SDO Read Timing (Not to Scale)
10
DS284PP2
DS284PP2
t 17 t 10 MODE
(Input)
RES
(Input)
t 11 t 13 t 12 t1
t 16
(Output)
CS
SCLK
(Output)
SDO
(Output)
t2 t 14
t 15
STOP BIT
SDI
(Input from EEPROM)
LAST 8 BITS
Data from EEPROM
Figure 3. CS5460A Auto-Boot Sequence Timing
CS5460A
11
CS5460A
2. GENERAL DESCRIPTION
The CS5460A is a CMOS monolithic power measurement device with an energy computation engine. The CS5460A combines a programmable gain amplifier, two modulators, two high rate filters, system calibration, and power calculation functions to compute Energy, VRMS, IRMS, and Instantaneous Power. The CS5460A is designed for power measurement applications and is optimized to interface to a shunt or current transformer to measure current, and a resistive divider or transformer to measure voltage. To accommodate various input voltage levels, the current channel includes a programmable gain amplifier (PGA) which provides either 150 mVRMS or 30 mVRMS as the full-scale input level. The CS5460A includes two high-rate digital filters which output data at a (MCLK/K)/1024 output word rate (OWR). To facilitate communication to a microcontroller, the CS5460A includes a simple three-wire serial interface which is SPITM and MicrowireTM compatible. The serial port has a Schmitt Trigger input on its serial clock (SCLK) to allow for slow rise time signals.
2.1 Theory of Operation
The CS5460A is designed to operate from a single +5 V supply or dual 2.5 V supplies. It provides a 30 mVRMS or 150 mVRMS range for the current channel and to provide a 150mVRMS range for the voltage channel. With single +5 V supply on VA+/-, the CS5460A accommodates common mode signals between -0.25 V and VA+. Figure 4 shows the CS5460A connected to a service to measure power in a single-phase 2-wire system while operating in a single supply configuration. Figure 5 shows the CS5460A configured to measure power in a single-phase 3-wire system.
5 k N N L L 500 470 nF 500 100 F 0.1 F 10 0.1 F 14 VA+
CS5460A
10 k
M:1
RPV*
3 VD+
9
Voltage Transformer
CPV *
R2 R1
VIN+
PFMON CPUCLK XOUT
17 2 1 2.5 MHz to 20 MHz Optional Clock Source
RPV*
10 15
VINIIN-
XIN
24
Alternate Sensor Options
N L RS N:1 RB
Current Transformer
RP I *
RESET CS SDI 16 CP *
I
19 7 23 6 5 20 22 21 Serial Data Interface
RP I *
IIN+ VREFIN VREFOUT VA13
SDO SCLK INT EDIR EOUT DGND 4
12
11
0.1 F
To Service
* Refer to Input Protection
- Section 4.13
Figure 4. Typical Connection Diagram (One-Phase 2-Wire) 12 DS284PP2
CS5460A
5 k L1 N L2 500 500 100 F 0.1 F 10 0.1 F 10 k
470 nF
14 VA+ CS5460A
3 VD+
9 CPV * R1 R2 R1 R2 CPV * 10 16 RPI * RS CPI * CPI *
VIN+
17 PFMON 2 CPUCLK 1 XOUT 24
2.5 MHz to 20 MHz Optional Clock Source
VINIIN+
XIN
RESET
19
15
RPI *
IIN-
12 VREFIN 11 VREFOUT
VA13
7 CS 23 SDI 6 SDO 5 SCLK 20 INT 22 EDIR 21 EOUT
Serial Data Interface
0.1 F DGND 4
To Service
To Service
* Refer to Input Protection - Section 4.13
Figure 5. Typical Connection Diagram (One-Phase 3-Wire)
2.2 Performing Measurements
The CS5460A performs measurements of instantaneous current, instantaneous voltage, instantaneous power, energy, RMS current, and RMS voltage. These measurements are output as 24-bit signed and unsigned data formats as a percentage of full scale. This means that the 24-bit data words in the CS5460A output registers represent values between 0 and 1 (for unsigned output registers) or between -1 and +1 (for signed output registers). A register value of 1 represents the maximum possible value. Note that a value of 1.0 is never actually obtained in the registers of the CS5460A. As an illustration, in any of the signed output registers, the maximum register value is [(2^23 - 1) / (2^23)] = 0.999999880791. The flow of data to perform these calculations is shown in Figure 6. After each A/D conversion, the CRDY bit will be asserted in the Status Register, and the INT pin will also become active if the CRDY bit is unmasked. This assertion of CRDY bit indicates that new instantaneous voltDS284PP2
age, current samples have been collected, and they are multiplied together to provide a corresponding instantaneous power sample. The VRMS, IRMS, and energy calculations are updated every N conversions (which is known as 1 "computation cycle") where N is the content of the Cycle Count register. At the end of each computation cycle, the DRDY bit in the Status and Mask register will be set, and the INT pin will become active if the DRDY bit is unmasked. DRDY is set only after each computation cycle has completed, whereas the CRDY bit is asserted after each individual A/D conversion. When these bits are asserted, they must be cleared by the user before they can be asserted again. If the Cycle Count Register value (N) is set to 1, all output calculations are instantaneous, and DRDY will indicate when instantaneous calculations are finished, just like the CRDY bit. For the RMS results to be valid, the Cycle-Count Register must be set to a value greater than 10.
13
CS5460A
VDCoff* V gn *
V*
VACoff*
VOLTAGE
DELAY REG
SINC 2
DELAY REG
FIR
HPF
+
x
x
-
SINC 2
N
V RMS *
APF Configuration Register * PC[6:0] Bits
Poff*
N x
TBC *
+
P*
x
/ 4096
E* E out E dir
E to F
PULSE-RATE* CURRENT
SINC 4
FIR
HPF
+
x
x
-
SINC 2
N
I RMS *
APF
IDCoff* I gn *
I*
IACoff*
* DENOTES REGISTER NAME
Figure 6. Data Flow.
Table 1 provides an example detailing the output linearity. A computation cycle is derived from the master clock and its frequency is (MCLK/K)/(1024*N). Under default conditions with a 4.096 Mhz clock at XIN, instantaneous A/D conversions for voltage, current, and power are performed at a 4000 Hz rate, whereas IRMS, VRMS, and energy calculations are performed at a 1 Hz rate.
of several result registers. The first 8 SCLKs are used to clock in the command to determine which register is to be read. The last 24 SCLKs are used to read the desired register. After reading the data, the serial port returns to the command mode, where it waits for a new command to be issued.
2.2.2 Multiple Computation Cycles (C = 1)
Based on the information provided in the Cycle Count register, computation cycles are repeatedly performed on the voltage and current channels (after every N conversions). Computation cycles cannot be started/stopped on a per channel basis. After each computation cycle is completed, DRDY is set. Thirty-two SCLKs are then needed to read a register. The first 8 SCLKs are used to clock in the command to determine which results register is to be read. The last 24 SCLKs are used to read the calculation result. While in this mode, the user may choose to acquire only the calculations required for the application as DRDY rises and falls to indicate the availability of a new data. The RMS calculations undergo a Sinc2 operation prior to their square root operation. Therefore, the first output for each channel will be invalid (i.e. all RMS calculations are invalid in the single compu-
2.2.1 Single Computation Cycle (C = 0)
Based on the information provided in the Cycle Count register, a single computation cycle is performed after the user transmits the single conversion cycle command. After the computations are complete, DRDY is set. Thirty-two SCLKs are then needed to acquire a calculation result from one
Energy Vrms 2:1 0.1% of reading 24-bits Irms 500:1 0.1% of reading
Range Max Input Linearity (After Calibration) Output word
1000:1 0.1% of reading
See Analog Characteristics
Table 1. Output Linearity after Calibration with MCLK = 4.096 MHz, K = 1, N = 4000 14
DS284PP2
CS5460A
tation cycle routine and the first RMS calculations will be invalid in the continuous computation cycle). All energy calculations will be valid since energy calculations do not require this Sinc2 operation. nel, then the all-pass filter can be used in the voltage channel to match the phase delay that is naturally introduced by the high-pass filter.
3. SERIAL PORT OVERVIEW
The CS5460A's serial port incorporates a state machine with transmit/receive buffers. The state machine interprets 8 bit command words on the rising edge of SCLK. Upon decoding of the command word the state machine performs the requested command or prepares for a data transfer of the addressed register. Request for a read requires an internal register transfer to the transmit buffer, while a write waits until the completion of 24 SCLKs before performing a transfer. The internal registers are used to control the ADC's functions. All registers are 24-bits in length. Figure 20 summarizes the internal registers available to the user. The CS5460A is initialized and fully operational upon power-on. After a power-on, serial port initialization, or reset, the serial port state machine is initialized into command mode where it waits to receive a valid command (the first 8-bits clocked into the serial port). Upon receiving and decoding a valid command word, the state machine instructs the converter to either perform a system operation, or transfer data to or from an internal register. The user should refer to the "Commands" section to decode all valid commands.
0.5 0 -0.5
2.3 High Rate Digital Filters
Referring to Figure 6, the high rate filter on the voltage channel is implemented as a fixed Sinc2 filter, compensated by a short length FIR. When the converter is driven with a 4.096 MHz clock (K=1), the filter has a magnitude response as shown in Figure 7. Note that the filter's response scales with MCLK frequency and K. The current channel contains a Sinc4 filter, compensated by a short length FIR. When the converter is driven with a 4.096 MHz clock (K=1) the composite filter response is given in Figure 8.
2.4 High-Pass Filters
A digital high-pass filter in both channels can be enabled to remove the DC content from the input signal before the energy calculations are made. These filters are activated by enabling certain bits in the configuration register. If the user wants to use the high-pass filters on just one of the two channels, then the user should apply the all-pass filter option to the other channel. For example, if high-pass filter is needed for voltage channel, but not the current chan0.5
0.0
Gain (dB)
-0.5
-1.0
Gain (dB)
0 200 400 600 800 1000 1200 1400 1600 1800 2000
-1 -1.5 -2 -2.5 0
-1.5
-2.0
-2.5 Frequency (Hertz)
200
400
600
800
1000 1200
1400 1600
1800 2000
Frequency (Hertz)
Figure 7. Voltage Input Filter Characteristics DS284PP2
Figure 8. Current Input Filter Characteristics 15
CS5460A
3.1 Commands (Write Only)
All command words are 1 byte in length. Commands that write to a register must be followed by 1, 2, or 3 bytes of register data. Commands that read from registers initiate 3 bytes of register data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent to SDI which can execute before the original read is completed). This allows for "chaining" commands.
3.1.1 Start Conversions
B7 1 B6 1 B5 1 B4 0 B3 C B2 0 B1 0 B0 0
This command indicates to the state machine to begin acquiring measurements and calculating results. The device has two modes of acquisition. C= Modes of measurement 0 = Perform a single computation cycle 1 = Perform continuous computation cycles
3.1.2 SYNC0 Command
B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 0
This command is the end of the serial port re-initialization sequence. The command can also be used as a NOP command. The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands followed by a SYNC0 command.
3.1.3 SYNC1 Command
B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 1
This command is part of the serial port re-initialization sequence. The command can also serve as a NOP command.
3.1.4 Power-Up/Halt
B7 1 B6 0 B5 1 B4 0 B3 0 B2 0 B1 0 B0 0
If the device is powered-down, this command will power-up the device. When powered-on, no computations will be running. If the part is already powered-on, all computations will be halted.
16
DS284PP2
CS5460A
3.1.5 Power-Down
B7 1 B6 0 B5 0 B4 S1 B3 S0 B2 0 B1 0 B0 0
The device has two power-down modes to conserve power. If the chip is put in stand-by mode all circuitry except the clock generator is turned off. S1,S0 Power-down mode 00 = Reserved 01 = Halt and enter stand-by power saving mode. This mode allows quick power-on time 10 = Halt and enter sleep power saving mode. This mode requires a slow power-on time 11 = Reserved
3.1.6 Calibration
B7 1 B6 1 B5 0 B4 V B3 I B2 R B1 G B0 O
The device has the capability of performing a system AC offset calibration, DC offset calibration, AC gain calibration, and DC gain calibration. The user can calibrate the voltage channel, the current channel, or both channels at the same time. Offset and gain calibrations should NOT be performed at the same time (must do one after the other). For a given application, if DC gain calibrations are performed, then AC gain calibration should not be performed (and vice-versa). The user must supply the proper inputs to the device before initiating calibration. V,I Designates calibration channel 00 = Not allowed 01 = Calibrate the current channel 10 = Calibrate the voltage channel 11 = Calibrate voltage and current channel simultaneously Specifies AC calibration (R=1) or DC calibration (R=0) Designates gain calibration 0 = Normal operation 1 = Perform gain calibration Designates offset calibration 0 = Normal operation 1 = Perform offset calibration
R G
O
DS284PP2
17
CS5460A
3.1.7 Register Read/Write
B7 0 B6 W/R B5 RA4 B4 RA3 B3 RA2 B2 RA1 B1 RA0 B0 0
This command informs the state machine that a register access is required. On reads the addressed register is loaded into the output buffer and clocked out by SCLK. On writes the data is clocked into the input buffer and transferred to the addressed register on the 24 th SCLK. W/R Write/Read control 0 = Read register 1 = Write register Register address bits. Binary encoded 0 to 31. All registers are 24 bits in length. Address 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 . . 10111 11000 11001 11010 11011 11100 11101 . . 11111 Name Config Ioff Ign Voff Vgn Cycle Count Pulse-Rate I V P E IRMS VRMS TBC Poff Status IACoff VACoff Res Description Configuration Register Current offset calibration Current gain calibration Voltage offset calibration Voltage gain calibration Number of conversions to integrate over (N) Used to calibrate/scale the energy to frequency output Last current value Last voltage value Last Power value Total energy value of last cycle RMS current value of last cycle RMS voltage value of last cycle Timebase Calibration Power Offset Register Status Register AC Current Offset Register AC Voltage Offset Register Reserved
RA[4:0]
Res Res Test Mask Res Ctrl Res
Reserved Reserved Reserved Mask Register Reserved Control Register Reserved
Res
Reserved
These Registers are for Internal Use only and should not be written to.
18
DS284PP2
CS5460A
3.2 Serial Port Interface Pins
The CS5460A's serial interface consists of four control lines: CS, SDI, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. SDI, Serial Data In, is the data signal used to transfer data to the converters. SDO, Serial Data Out, is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1. SCLK, Serial Clock, is the serial bit-clock which controls the shifting of data to or from the ADC's serial port. The CS pin must be held at logic 0 before SCLK transitions can be recognized by the port logic. To accommodate opto-isolators SCLK is designed with a Schmitt-trigger input to allow an opto-isolator with slower rise and fall times to directly drive the pin. Additionally, SDO is capable of sinking or sourcing up to 5 mA to directly drive an opto-isolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA.
3.3.1 Register Write
Command words instructing a register write must be followed by 24 bits of data. For instance, to write the Configuration Register, the user would transmit the command (0x40) to initiate the write. The CS5460A will then acquire the serial data input from the (SDI) pin when the user pulses the serial clock (SCLK) 24 times. Once the data is received the state machine would write the data to the Configuration Register and return to the command mode.
3.3.2 Register Read
Command words instructing a register read may be terminated at 8-bit boundaries (e.g., read transfers may be 8, 16, or 24 bits in length). Also data register reads allow "command chaining". For example, a command word instructs the state machine to read a signed output register. After the user pulses SCLK for 16-bits of data, a write command word (e.g., to clear the Status Register) may be pulsed on to the SDI line at the same time the remaining 8-bits of data are pulsed from the SDO line. When a command involves a write operation, the serial port will continue to clock in the data bits (MSB first) on the SDI pin for the next 24 SCLK cycles. When a read command is initiated, the serial port will start transferring register content bits serial (MSB first) on the SDO pin for the next 8, 16, or 24 SCLK cycles depending on the command issued. The micro-controller is allowed to send a new command while reading register data. The new command will be acted upon immediately and could possibly terminate the register read. During the read cycle, the SYNC0 command (NOP) should be strobed on the SDI port while clocking the data from the SDO port.
3.3 Serial Read and Write
The state machine decodes the command word as it is received. Data is written to and read from the CS5460A by using the Register Read/Write command. Figure 9 illustrates the serial sequence necessary to write to, or read from the serial port's buffers. As shown in Figure 9, a transfer of data is always initiated by sending the appropriate 8-bit command (MSB first) to the serial port (SDI pin). It is important to note that some commands use information from the Cycle-Count Register and Configuration Register to perform the function. For those commands, it is important that the correct information is written to those registers first.
DS284PP2
19
CS5460A
CS
SCLK MSB SDI Command Time 8 SCLKs Data Time 24 SCLKs LSB MSB LSB
Write Cycle
CS
SCLK MSB SDI
Command Time 8 SCLKs
LSB
MSB
LSB
SDO Data Time 24 SCLKs
Read Cycle
Figure 9. Command and Data Word Timing
20
DS284PP2
CS5460A
3.4 Serial Port Initialization
The serial port can be initialized to the command mode in several different ways. One of these is by issuing the serial port initialization sequence. The serial port initialization sequence involves clocking 3 (or more) SYNC1 command bytes (0xFF) followed by one SYNC0 command byte (0xFE). There are other valid ways to set the chip into command mode. For completeness, all of the possible initialization actions are listed here: 1) With power already on, issue Serial Port Initialization Sequence (described above). Or, 2) Power the chip on. 3) Wake the CS5460A out of Sleep Mode 4) Wake the CS5460A out of Stand-By Mode 5) Hardware Reset 6) Software Reset Performing any of these actions will place the chip in the command mode, where it waits until a valid command is received. The RESET signal is asynchronous, requiring no MCLKs for the part to detect and store a reset event. The RESET pin is a Schmitt Trigger input, allows it to tolerate slow rise times and/or noisy control signals. (This can often turn out to be the case, after a power failure or brown-out on the power line.) Once the RESET pin is inactive, the internal reset circuitry remains active for 5 MCLK cycles to insure resetting the synchronous circuitry in the device. The modulators are held in reset for 12 MCLK cycles after RESET becomes inactive. After a hardware or software reset, the internal registers (some of which drive output pins) will be reset to their default values on the first MCLK received after detecting a reset event (see Table 2). The CS5460A will then wait for a valid command on the serial port. The reader should refer to the section titled "Register Description" for a complete description of the registers listed in Table 2.
3.5 System Initialization
A software or hardware reset can be initiated at any time. The software reset is initiated by writing a logic 1 to the RS (Reset System) bit in the configuration register, which automatically returns to logic 0 after reset. At the end of the 32nd SCLK (i.e., 8 bit command word and 24 bit data word) internal synchronization delays the loading of the configuration register by 3 or 4 DCLK (MCLK/K). Then the reset circuit initiates the reset routine on the 1st falling edge of MCLK. A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns.
Configuration Register: Offset Register: Gain Registers Pulse-Rate Register: Cycle-Counter Register: Timebase Register: Status Register: Mask Register: Control Register: AC Current Offset Register: AC Voltage Offset Register: Power Offset Register: All Data Registers: All Unsigned Data Registers
0x000001 0x000000 0x400000 0x0FA000 0x000FA0 0x800000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000
Table 2. Internal Registers Default Value
DS284PP2
21
CS5460A
4. FUNCTIONAL DESCRIPTION 4.1 Pulse-Rate Output
As an alternative to reading the energy through the serial port, the EOUT and EDIR pins provide a simple interface with which signed energy can be accumulated. Each EOUT pulse represents a predetermined magnitude of energy. The accompanying EDIR output represents the sign of the energy. With MCLK = 4.096 MHz, K = 1, the pulses will have an average frequency equal to the frequency setting in the Pulse Rate Register when the input levels into the voltage and current channels cause full-scale readings in the instantaneous voltage and current registers. When MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate that one would expect to get with MCLK/K = 4.096 MHz by a factor of 4.096 MHz / (MCLK / K) to get the actual output pulse-rate. EXAMPLE #1: Suppose that we want the pulse-frequency on the EOUT pin to be `IR' = 100 pulses per second (100 Hz) when the RMS-voltage/RMS-current levels on the power line are 220 V and 15 A respectively, noting that the maximum rated levels on the power line are 250 V and 20 A. We also assume that we have calibrated the CS5460A voltage/current channel inputs such that a DC voltage level of 250 mV across the voltage/current channels will cause full-scale readings of 1.0 in the CS5460A Instantaneous Voltage and Current Registers as well as in the RMS-Voltage and RMS-Current Registers. We want to find out what frequency value we should put into the CS5460A's pulse-rate register (call this value `PR') in order to satisfy this requirement. Our first step is to set the voltage and current sensor gain constants, KV and KI, such that there will be acceptable input voltage levels on the inputs when the power line voltage and current levels are at the maximum values of 250 V and 20 A, respectively. We need to calculate KV and KI in order to determine the appropriate ratios of the voltage/current
22
transformers and/or shunt resistor values to use in the front-end voltage/current sensor networks. We assume here that we are dealing with a sinusoidal AC power signal. For a sinewave, the largest RMS value that can be accurately measured (without over-driving the inputs) will register at ~0.7071 of the maximum DC input level. Since power signals are often not perfectly sinusoidal in real-world situations, and to provide for some over-range capability, we will set the RMS-Voltage and RMS-Current Registers to measure at 0.6 when the RMS-values of the line-voltage and line-current levels are at 250 V and 20 A. Therefore, when the RMS registers measure 0.6, the voltage level at the inputs will be 0.6 x 250 mV = 150 mV. We now find our sensor gain constants, KV and KI, by demanding that the voltage and current channel inputs should be at 150 mV RMS when the power line voltage and current are at the maximum values of 250 V and 20 A. KV = 150 mV / 250 V = 0.0006 KI = 150 mV / 20 A = 0.0075 Ohms These sensor gain constants can help determine the ratios of the transformer or resistor-divider sensor networks. We now use these sensor gain constants to calculate what the input voltage levels will be on the CS5460A inputs when the line-voltage and line-current are at 220 V and 15 A. We call these values VVnom and VInom. VVnom = KV * 220 V = 132 mV VInom = KI * 15 A = 112.5 mV The pulse rate on EOUT will be at `PR' pulses per second (Hz) when the RMS-levels of voltage/current inputs are at 250 mV. When the voltage/current inputs are set at VVnom and VInom, we want the pulse rate to be at `IR' = 100 pulses per second. IR will be some percentage of PR. The percentage is defined by the ratios of VVnom/250 mV and VInom/250 mV with the following formula:
DS284PP2
CS5460A
V Vnom V Inom PulseRate = IR = PR ----------------- ----------------250mV 250mV
We can rearrange the above equation and solve for PR. This is the value that we put into the pulse-rate register.
100Hz IR PR = ------------------------------------------- = ----------------------------------------------132mV 112.5mV V Vnom V Inom ----------------- x --------------------------------------- x ----------------250mV 250mV 250mV 250mV
where we again have calculated our sensor gains such that the maximum line-voltage and line-current levels will measure as 0.6 in the RMS-voltage and RMS-current registers. We can now calculate the required Pulse-Rate Register setting by using the following equation:
pulses 1hr 1kW 250mV 250mV PR = 500 ------------------ ------------- ----------------- ----------------- ----------------KI kW hr 3600s 1000W KV
Therefore we set the Pulse-Rate Register to ~420.875 Hz. Therefore, the Pulse-Rate Register would be set to 0x00349C. The above equation is valid when current channel is set to x10 gain. If current channel gain is set to x50, then the equation becomes:
IR PR = ---------------------------------------V Vnom VInom ------------------ x -------------250mV 50mV
Therefore PR = ~1.929 Hz. Note that the Pulse-Rate Register cannot be set to a frequency of exact 1.929 Hz. The closest setting that the Pulse-Rate register can obtain is 0x00003E = 1.9375. To improve the accuracy, either gain register can be programmed to correct for the round-off error in PR. This value would be calculated as
PR Ign or Vgn = ------------ 1.00441 = 0x404830 1.929
where it is assumed that the current channel has been calibrated such that the current-register will read at full-scale when the input voltage across the IIN+ and IIN- inputs is 50 mV (DC). EXAMPLE #2: Suppose that instead of being given a desired frequency of pulses per second to be issued at a specific voltage/current level, we are given a desired number of pulses per unit energy to be present at EOUT, given that the maximum line-voltage is at 250 V (RMS) and the maximum line-current is at 20 A (RMS). For example, suppose that the required number of pulses per kW-hr is specified to be 500 pulses/kW-hr. In such a situation, the nominal line voltage and current do not determine the appropriate pulse-rate setting. Instead, the maximum line-voltage and line-current levels must be considered. We use the given maximum line-voltage and line-current levels to determine KV and KI as previously described to get: KV = 150 mV / 250 V = 0.0006 KI = 150 mV / 20 A = 0.0075 Ohms
4.2 Multi-Phase Option for Pulse Output
To allow for a simpler interface in a multi-phase system, the EOUT and EDIR pins can be connected together and used in a wire-AND configuration. In this type of operation, the EWA bit in the Configuration Register must be activated (set to 1), and the user must supply external pull-up devices in order to pull the wire-AND output to logic-high. See Figure 11. The parts must be driven with the same clock and programmed with different phases (see PH[1:0] bits in the Configuration Register). The pulse width and the pulse separation is an integer multiple of system clocks (approximately equal to 1/8 of the period of the contents of the pulse-rate register). The maximum frequency is therefore MCLK/K/8. A timing diagram for a multi-phase system is shown in Figure 10.
DS284PP2
23
CS5460A
Phase - 00 t Phase - 01
Phase - 10
t Phase - 11
t
@ Pulse-Rate Register Period =
8
N MCLK/K
for Integer N
Figure 10. Multi-Phase System (Normal Mode only)
VDD
5K CS5460A EOUT
5K
EOUT EDIR EDIR
CS5460A EOUT EDIR
CS5460A EOUT EDIR
Figure 11. Option for wire and configuration of EOUT and EDIR pins for multi-phase metering 24 DS284PP2
CS5460A
4.3 Pulse Output for Normal Mode, Stepper Motor Mode and Mechanical Counter Mode
The EOUT and EDIR output formats can be modified so that the time duration of the pulses is increased to the point that they can drive either an electro-mechanical counter or a stepper motor. These modes are controlled by setting certain bits in the Control Register. When energy is negative, pulses appear on EDIR. It is up to the user to insure that pulses will not occur at a rate faster than the 128 ms pulse duration, or faster than the mechanical counter can accommodate. The user must make sure that the Pulse-Rate Register is set to an appropriate value. Because the duration of each pulse is set to 128 ms, the maximum output pulse frequency is limited to ~7.8 Hz. (See Figure 12.) For values of MCLK / K different than 4.096 MHz, the duration of one pulse is (128 * 4.096 MHz)/(MCLK / K) milliseconds.
4.3.1 Normal Mode
Referring to the description of the Control Register in Section 5., REGISTER DESCRIPTION, if both the MECH and STEP bits are set to `0', the EOUT and EDIR pulse outputs for a single CS5460A have the same format as the "Phase - 00" signal shown in Figure 10--active-low pulses with very short width. When energy is positive, EDIR is always high. When energy is negative, EDIR has the same output as EOUT. When MCLK/K is not equal to 4.096 MHz, the user can predict the pulse-rate
4.3.3 Stepper Motor Mode
Setting the STEP bit in the control register to `1' and the MECH bit to `0' transforms the EOUT and EDIR pins into two stepper motor phase outputs. When an energy pulse occurs, one of the outputs changes state. When the next energy pulse occurs, the other output changes state. The direction the motor will rotate is determined by the order of the state changes. When energy is positive, EOUT will lead EDIR. When energy is negative, EDIR will lead EOUT. See Figure 13.
4.3.2 Mechanical Counter Mode
Setting the MECH bit in the control register to `1' and the STEP bit to `0' enables wide stepping pulses for mechanical counters and similar appliances. In this mode, active-low pulses are 128 ms wide when using a 4.096 MHz crystal and K=1. When energy is positive, the pulses appear on EOUT.
128 ms EOUT EDIR Positive Energy
4.4 Auto-Boot Mode Using EEPROM
The CS5460A has a MODE pin. When the MODE pin is set to logic low, the CS5460A is in normal operating mode, called command mode. This mode denotes the normal operation of the part, that
128 ms Negative Energy
Figure 12. Mechanical Counter Mode on EOUT and EDIR
EOUT EDIR Positive Energy Negative Energy
Figure 13. Stepper Motor Mode on EOUT and EDIR
DS284PP2
25
CS5460A
has been described so far. But when this pin is set to logic high, the CS5460A auto-boot mode is enabled. In auto-boot mode, the CS5460A is configured to request a memory download from an external serial EEPROM. The download sequence is initiated by driving the /RESET pin to logic high. Auto-Boot mode allows the CS5460A to operate without the need for a microcontroller. Note that if the MODE pin is left unconnected, it will default to logic low because of an internal pull-down on the pin. Figure 14 shows the typical connections between the CS5460A and a serial EEPROM for proper auto-boot operation. In this mode, /CS and SCLK are driven outputs. SDO is always an output. During the auto-boot sequence, the CS5460A drives /CS low, provides a clock output on SCLK, and drives out-commands on SDO. It receives the EEPROM data on SDI. The serial EEPROM must be programmed with the user-specified commands and register data that will be used by the CS5460A to initialize and begin conversions. Figure 14 also shows the external connections that would be made to a calibrator device, such as a PC or custom calibration board. When the metering system is installed, the calibrator would be used to control calibration and/or to program user-specified commands and calibration values into the EEPROM. The user-specified commands/data will determine the CS5460A's exact mode of operation once the auto-boot sequence is initiated. Any of the valid commands can be used. For example, the EEPROM can be programmed so that it would first send out commands that write calibration values to the calibration registers inside the CS5460A, then it could enable the EOUT and EDIR functionality and set a Pulse-Rate Register value. Finally, the code can send out the commands to initiate continuous conversions, and to set the pulse-output mode to specific format (e.g., set the MECH bit in the Control Register). The serial data for such a sequence is shown below in single-byte hexidecimal notation: 40 00 00 61 ;In configuration Register, turn high-pass filters on, set K = 1. ;Write value of 0x7FC4A9 to Current Gain Register. ;Write value of 0xFFB253 to DC Voltage Offset Register. ;Set Pulse Rate Register to 0.625 Hz.
44 7F C4 A9 46 7F B2 53 4C 00 00 14
VD+
CS5460A
5K /EOUT /EDIR SCK SDI SDO MODE /CS
5K
EEPROM
SCK SO SI /CS
Connector to Calibrator
Figure 14. Typical Interface of EEPROM to CS5460A
26
DS284PP2
CS5460A
E8 78 00 01 40 ;Start continuous conversions. ;Write stop bit to CS5460A to terminate auto-boot sequence, and set the EOUT pulses to Mechanical Counter Mode. * National Semiconductor NM25C040M8 NM25020M8 * Xicor X25040SI These types of serial EEPROMs expect a specific 8-bit command word (00000011) in order to perform a memory download. The CS5460A has been hardware programmed to transmit this 8-bit command word to the EEPROM at the beginning of the auto-boot sequence. The auto-boot sequence is terminated by writing a `1' to the STOP bit in the CS5460A's Control Register. This action is performed as the last command in the EEPROM command sequence. Once this event occurs, SCLK stops, and /CS rises, thereby reducing power consumed by the EEPROM. When the CS5460A is commanded by the EEPROM to perform a certain operation, it will continue to execute that operation after the STOP bit has been received. In the above example, the `continuous conversion' command (0xE8) is issued from the EEPROM, and therefore the CS5460A will continue performing conversions even after the STOP bit is written.
This data from the EEPROM will drive the SDI pin of the CS5460A during the auto-boot sequence. The following sequence of user-controlled events will cause the CS5460A to enter auto-boot mode: (A simple timing diagram for this sequence is shown below in Figure 15.) After the CS5460A has been powered on and has been allowed to initialize, if the MODE pin is set to logic high, then changing the /RESET pin from active state to inactive state (low to high) will cause CS5460A to bring the /CS pin low, and then issue the standard block read command out of the SDO line. Then the CS5460A will continue to issue SCLKs, to accept data from the EEPROM. A more detailed timing diagram can be found in the SWITCHING CHARACTERISTICS section of this data sheet. Several industry-standard serial EEPROMs that will successfully run auto-boot with the CS5460A are listed below: * Atmel AT25010 AT25020 AT25040
MODE RES CS SCLK SDO SDI 5460A Commands Stop EE Read Address 0
Figure 15. Timing Diagram for Auto-Boot Sequence
DS284PP2
27
CS5460A
4.5 Interrupt and Watchdog Timer 4.5.1 Interrupt
The INT pin is used to indicate that an event has taken place in the converter that needs attention. These events inform the system about operation conditions and internal error conditions. The INT signal is created by combining the Status register with the Mask register. Whenever a bit in the Status register becomes active, and the corresponding bit in the Mask register is a logic 1, the INT signal becomes active. The interrupt condition is cleared when the bits of the Status Register are returned to their inactive state. Step H1 - Disable all interrupts. Step H2 - Branch to the proper interrupt service routine. Step H3 - Clear the Status Register by writing back the value read in step H0. Step H4 - Re-enable interrupts. Step H5 - Return from interrupt service routine. This handshaking procedure insures that any new interrupts activated between steps H0 and H3 are not lost (cleared) by step H3.
4.5.1.3 INT Active State
The behavior of the INT pin is controlled by the SI1 and SI0 bits of the configuration register. The pin can be active low (default), active high, active on a return to logic 0 (pulse-low), or active on a return to logic 1 (pulse-high).
4.5.1.1 Clearing the Status Register
Unlike the other registers, the bits in the Status Register can only be cleared (set to logic 0). When a word is written to the Status Register, any 1s in the word will cause the corresponding bits in the Status Register to be cleared. The other bits of the Status Register remain unchanged. This allows the clearing of particular bits in the register without having to know the state of the other bits. This mechanism is designed to facilitate handshaking and to minimize the risk of losing events that haven't been processed yet.
4.5.1.4 Exceptions
The IC (Invalid Command) bit of the Status Register can only be cleared by performing the port initialization sequence. This is also the only Status Register bit that is active low. To properly clear the WDT (WatchDog Timer) bit of the Status Register, first read the Energy Register, then clear the bit in the Status Register.
4.5.1.2 Typical use of the INT pin
The steps below show how interrupts can be handled. * Initialization: Step I0 - All Status bits are cleared by writing FFFFFF (Hex) into the Status Register. Step I1 - The conditional bits which will be used to generate interrupts are then written to logic 1 in the Mask register. Step I3 - Enable interrupts. * Interrupt Handler Routine: Step H0 - Read the Status Register.
4.5.2 Watch Dog Timer
The Watch Dog Timer (WDT) is provided as means of alerting the system that there is a potential breakdown in communication with the micro-controller. By allowing the WDT to cause an interrupt, a controller can be brought back, from some unknown code space, into the proper code for processing the data created by the converter. The time-out is preprogrammed to approximately 5 seconds. The countdown restarts each time the Energy register is read. Under typical situations, the Energy register is read every second. As a result, the WDT will not time out. Other applications that use the watchdog timer will need to ensure that the EnDS284PP2
28
CS5460A
ergy register is read at least once in every 5 second span. abled. This signal range is designed to handle low level signals from a shunt sensor.
4.6 Oscillator Characteristics
XIN and XOUT are the input and output, respectively, of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator, as shown in Figure 16. The oscillator circuit is designed to work with a quartz crystal or a ceramic resonator. To reduce circuit cost, two load capacitors C1 are integrated in the device, one between XIN and DGND, one between XOUT and DGND. Lead lengths should be minimized to reduce stray capacitance. With these load capacitors, the oscillator circuit is capable of oscillation up to 20 MHz. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. The CS5460A can be driven by a clock ranging from 2.5 to 20 MHz. The user must appropriately set the K divider value such that the internal DCLK will run somewhere between 2.5 MHz and 5 MHz. The K divider value is set with the K[3:0] bits in the Configuration Register. As an example, if XIN = MCLK = 15 MHz, and K is set to 5, then DCLK is 3 MHz, which is a valid value for DCLK. Note that if the K[3:0] bits are all set to zero, the value of the K divider value is 16.
4.8 Voltage Reference
The CS5460A is specified for operation with a +2.5 V reference between the VREFIN and VApins. The converter includes an internal 2.5 V reference (60 ppm/C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used.
4.9 Calibration 4.9.1 Overview of Calibration Process
The CS5460A offers AC or DC calibration. The user decides which calibration is being performed by setting/clearing one or more of the 8 bits in the Calibration command word. Regardless of whether an AC or DC calibration is desired, there are two calibration modes: system offset and system gain. During calibration, the user must supply the input calibration signals to the "+" and "-" pins of the voltage-/current-channel input. These input calibration signals represent full-scale and ground input levels. Whether it is AC or DC calibration, the user must provide the positive full-scale reference signals to perform a system gain calibration, and a
XOUT C1
4.7 Analog Inputs
The CS5460A accommodates a full scale range of 150 mVRMS on both input channels. System calibration can be used to increase or decrease the full scale span of the converter as long as the calibration register values stay within the limits specified. See Section 4.9, Calibration, for more details. The current input channel has an input range of 30 mVRMS when the internal x50 gain stage is enDS284PP2
XIN C1
Oscillator Circuit
DGND
C1 = 22 pF
Figure 16. Oscillator Connection
29
CS5460A
ground-referenced signal to perform a system offset calibration. The differential voltage levels of the user-provided calibration signals must be within the specified voltage input limits (refer to "Differential Input Voltage Range" in Section 1., Characteristics and Specifications). The voltage level of these calibration input signals must be within the specified calibration limits for each specific calibration step and channel. are applied to the voltage/current signals very early in the signal path, and so the DC Offset Register value affects all CS5460A results. This is not true for the AC Offset. The AC Offset Registers only affect the results of the rms-voltage/rms-current calculations.
4.9.3 Calibration Sequence
The basic flow of the calibration sequence is to first apply the appropriate calibration signals to the "+" and "-" pins of the voltage/current channel inputs, and then the user must send the appropriate calibration command to the CS5460A. The calibration command is an 8-bit command. Various bits within this command specify the exact type of calibration that is to be performed (e.g., AC gain cal for voltage channel, DC offset cal for current channel, etc.) After the CS5460A is finished running its internal calibration, and storing the results in the appropriate calibration registers, the DRDY bit is set (in the Status Register) to indicate that the calibration sequence has been completed. Note that when the calibration command is sent to the CS5460A by the user, the device should NOT be running in conversion mode. The calibration will not run if the part is already running in either of the two available conversion modes. Figure 17 shows the basic setup for gain calibration. If a DC gain calibration is desired, the user should apply a DC voltage level that truly represents the absolute maximum voltage level that will be needs to be measured across the inputs.a DC voltage level that represents the desired absolute peak full-scale value. However, in many practical power metering situations, an AC signal is preferred over a DC signal to calibrate the gain. If the user decides to perform AC gain calibration instead of DC, the user should apply an AC reference signal that is set to the desired maximum RMS level. In general, the RMS level of the AC gain calibration signals will need to be significantly lower than the maximum output value of the instantaneous
DS284PP2
4.9.2 The Calibration Registers
Since both the voltage and current channels have separate offset and gain registers associated with them, the system offset or system gain can be performed on either channel without the calibration results from one channel affecting the other. Referring to Figure 6, it is important to note that for both the voltage channel and current channel, there are separate calibration registers for the AC and DC offset corrections. This is not true for gain corrections, as there is only one gain register per channel--AC and DC gain calibration results are stored in the same register. The results in the gain registers reflect either the AC or DC gain calibration results, whichever was performed most recently. Both a DC and AC offset can be applied to the system at the same time, but only one gain calibration can be applied to the system. The user must decide which type of gain calibration will be used: AC or DC, but not both. Therefore, the following six registers exist: * * * * * * Voltage Gain Register Current Gain Register DC Voltage Offset Register DC Current Offset Register AC Voltage Offset Register AC Current Offset Register
Referring to Figure 6, one should note that the AC Offset Registers affect the output results differently than the DC Offset Registers. The DC offset values
30
CS5460A
voltage and current registers in order to avoid clipping the signals when they reach their maximum peak value. For example, the largest sinusoid that can be used in AC calibration is one whose RMS-value is ~0.7071 of the value of the peak DC input voltage value. For the offset configuration, there is no difference between the AC and DC calibration signals, as the user should simply ground the voltage-/current-channel input(s) during this calibration. (See Figure 18.) The user should not try to run both an offset and gain calibration at the same time. This will cause undesirable calibration results.
4.9.4 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines the number of conversions averaged to obtain the calibration results. When N is increased by the user, the accuracy of the calibration results will increase. For DC offset/gain calibrations, the calibration sequence always takes at least N + 30 conversion cycles to complete. For AC offset/gain calibrations, the calibration sequence takes at least 6N + 30 A/D conversion cycles to complete, (about 6 computation cycles). For all calibrations (AC or DC), once a calibration cycle is complete, the DRDY bit is set and the results are stored in either the gain or offset registers.
4.9.5 Description of Calibration Algorithms
The algorithms for the AC and DC calibrations are shown in Figure 19. This figure applies to both the voltage channel and the current channel. The following descriptions of calibration algorithms will focus on the voltage channel, but apply equally to the current channel. The AC voltage gain calibration algorithm attempts to adjust the voltage gain register value so that the calibration reference signal level presented at the voltage inputs will result in a value of 0.6 in the RMS-voltage register. The level of the calibration signal is determined by the user. During AC voltage gain calibration, the value in the RMS-voltage register is divided into 0.6. This result is the AC gain calibration value, stored in the gain register.
Note:
+ AIN+ 0V + CM + AINXGAIN +
External Connections + Full Scale (DC or AC)
+
+ XGAIN
AIN+
AIN-
-
CM + -
Figure 17. System Calibration of Gain.
External Connections
Figure 18. System Calibration of Offset.
For proper calibration, it is assumed that the value of the Voltage/Current Gain Registers are set to 1.0 before running the gain calibration(s), and the value in the AC and DC Offset Registers is set to 0 before running calibrations. This can be accomplished by a software or hardware reset of the device. The values in the Voltage/Current Gain Registers do affect the results of the AC/DC gain calibrations.
DS284PP2
31
CS5460A
The idea of the AC offset calibration is to obtain an offset value that reflects the square of the RMS output level when the inputs are grounded. During normal operation, when the CS5460A is calculating the latest result for the RMS-Voltage Register, this AC offset register value will be subtracted from the square of each successive voltage sample in order to nullify the AC offset that may be inherent in the voltage-channel signal path. Note that the value in the AC offset register is proportional to the square of the AC offset. First, the inputs should be grounded by the user, and then the AC offset calibration command should be sent to the CS5460A. When the AC offset calibration sequence is initiated by the user, the most recent RMS-Voltage Register result is squared. This value is then subtracted from the square of each voltage sample that comes through the RMS data path. See Figure 19. After the user-provided calibration voltage has been applied to the inputs, the CS5460A determines the DC Gain Register value by averaging the output signal values over one computation cycle (N samples) and then dividing this average into 1. Therefore, after the DC voltage gain calibration has been executed, the instantaneous voltage register will read at full-scale when the DC level of the input signal is equal to the level of the DC calibration signal that was applied to the voltage channel inputs during the DC gain calibration. For example, if a 240 mV DC signal is applied to the voltage channel inputs during the DC gain calibration for the current channel, then the Instantaneous Voltage Register will measure at unity whenever a 240 mV DC level is applied to the voltage channel inputs. The DC offset register holds the negative of the simple average of N samples taken while the DC calibration was executed. The inputs should be grounded during DC offset calibration. The DC offset value is added to the signal path to nullify the DC offset in the system.
4.9.6 Is Calibration Required?
The CS5460A does not have to be calibrated. After the part is reset or powered on, the device is functional and can perform measurements without being calibrated. The output register values will be affected by the default values of the on-chip registers (Gain = 1.0, DC Offset = 0.0, AC Offset = 0). Although the device can be used without performing an offset or gain calibration, the accuracy and linearity specs of the CS5460A will not be valid until after a gain/offset calibration is performed. Note that the 0.1% linearity specs in this data sheet assume that the device has been calibrated with MCLK = 4.096 MHz, K = 1, and N = 4000.
to V*, I*, P*, E* Registers
In
Modulator
Filter
+
+ +
x
X
2
+
+ -
SINC
2
X
/N
V RMS*
DC Offset*
Gain*
/N
N
AC Offset*
2
X 1 x
-X 0.6 x
* Denotes readable/writable register
Figure 19. Calibration Data Flow 32 DS284PP2
CS5460A
4.9.7 Calibration Tips
To minimize digital noise, the user should wait for each calibration step to be completed before reading or writing to the serial port. After a calibration is performed, the offset and gain register contents can be read and stored externally. by the system micro-controller and recorded in memory. The same calibration words can be uploaded into the offset and gain registers of the converters when power is first applied to the system, or when the gain range on the current channel is changed. An offset calibration should be performed before a gain calibration. Each gain calibration depends on the zero calibration point obtained from the offset calibration. = 4.096 MHz and K=1, the range of the internal phase compensation ranges from -2.8 degrees to +2.8 degrees when the input voltage/current signals are at 60 Hz. In this condition, each step of the phase compensation register (value of one LSB) is ~0.04 degrees. For values of MCLK other than 4.096 MHz, these values for the span (-2.8 to +2.8 degrees) and for the step size (0.04 degrees) should be scaled by 4.096 MHz / (MCLK / K). For power line frequencies other than 60Hz (e.g., 50 Hz), the user can predict the values of the range and step size by converting the above values to time-domain, and then computing the new range and step size in terms of degrees with respect to the new line frequency. To calibrate the phase delay, the user may try adjusting the phase compensation bits while the CS5460A is in normal continuous conversion mode. Before doing so, the user should provide a purely resistive load (no inductance or capacitance) to the power line, such that nominal-level voltage and current signals from the power line are sensed into the voltage and current channels of the CS5460A. In this condition, any phase delay between the measured voltage and current signals is due only to phase delay introduced by the user's external voltage/current sensor circuitry. The objective is to adjust the phase compensation bits until the Energy Register value is maximized.
4.10 Phase Compensation
Bits 23 to 17 of the Configuration Register are used to program the amount of phase delay that is added to the voltage channel signal path. This phase delay is applied to the voltage channel signal in order to compensate for phase delay that is may be introduced by the user-supplied voltage and current sensor circuitry, which is external to the CS5460A. Voltage and current transformers, as well as other sensor equipment applied to the front-end of the CS5460A inputs can often introduce a phase delay in the system, which distorts the phase relationship between the voltage and current signals that are to be measured. The user can set the phase compensation bits to nullify this undesirable phase distortion between the two channels. The CS5460A does not provide automatic phase calibration. The user must determine the phase compensation empirically. The default value of the phase compensation bits is 0000000. With this default setting, the phase delay on the voltage channel is ~0.0215 degrees (assuming a 60 Hz power signal). Note that the 7-bit phase compensation word is a 2's complement binary number. With MCLK
DS284PP2
4.11 Time-Base Calibration Register
The Time-Base Calibration Register (notated as "TBC" in Figure 6) is used to compensate for slight errors in the XIN frequency. External oscillators and crystals have certain tolerances. If the user is concerned about improving the accuracy of the clock for energy measurements, the Time-Base Calibration Register can be manipulated to compensate for the frequency error. Note from Figure 6 that the TBC Register only affects the value in the Energy Register.
33
CS5460A
As an example, if the desired XIN frequency is 4.096 MHz, but the crystal is measured to actually be 4.091 MHz. The ratio of the desired frequency to the actual frequency is 4.096 MHz/4.091 MHz = ~1.00122219506. The TBC Register can be set to 1.0012223364 = 0x80280C(h), which is very close to the desired ratio. already provided to the VIN+ input pin. In Figure 5, if a voltage transformer is used as the voltage sensor, then a resistor RPV should be installed in series with the VIN+ pin. Figure 4 shows how the analog inputs are connected for a common-mode configuration. Figure 5 shows a differential configuration. A differential input configuration can be used, because the voltage/current channel inputs are able to accept input voltage levels all the way down to -250 mV below the potential of the VA- pin (which is normally connected to ground). Note that a differential configuration could have been used in Figure 4, and a common-mode input configuration could have been used in Figure 5. If the negative sides of the CS5460A input channels are not grounded (i.e., if VIN- and IIN- are connected in a differential configuration) then it is appropriate to put protection resistors on these inputs as well (see Figure 5). In fact, even in the common-mode configuration, protection resistors and filter caps may be placed on the VIN- and IIN- inputs in order to provide a more balanced configuration, to improve common-mode rejection of very high-frequency EMI. Capacitors CPV and CPI should be included to provide for attenuation of high-frequency noise that may be coupled into the input lines. In differential input configurations, such a capacitor should be added to the VIN- and IIN- pins in addition to the VIN+ and IIN+ pins. These capacitors should be placed in close proximity to the input pins for optimal protection against EMI. Values for RPV/I and CPV/I must be chosen with the approximate input lowpass cutoff frequency in mind. In general, the cutoff frequency should not be less than 10 times the roll-off frequencies of the internal voltage/current channel filters (see Figure 7 and Figure 8). From these figures we see that the internal voltage channel roll-off is at ~1400 Hz while the current channel roll-off is at ~1600 Hz. If the cutoff frequency of the external
4.12 Power Offset Register
Referring to Figure 6, note the Poff Register that appears just after the power computation. This register can be used to offset system power sources that may be resident in the system, but do not originate from the power line signal. These sources of extra energy in the system contribute undesirable and false offsets to the power/energy measurement results. For example, when a voltage signal is applied to the voltage channel inputs and the current channel has no line current, the current channel may still register a very small amount of current. This current measurement is cause by leakage of the voltage channel input signal into the current channel input signal path. The user can experimentally determine the amount of stray power that might be induced into the input pins, and then program the Power Offset Register to nullify the effects of this unwanted energy.
4.13 Input Protection and Filtering
In Figure 4 and Figure 5, note the series resistor RPI which is connected to the IIN+ input pin. This resistor is used to provide current-limit protection for the current-channel input pin in the event of a power surge or lightening surge. The voltage/current-channel inputs have surge-current limits of 100 mA. This applies to brief voltage/current spikes (<500 msec). The limit is 10 mA for DC input overload situations. The VIN+ pin does not need a protection resistor for the configurations shown in Figure 4 and Figure 5. This is because a resistive voltage-divider is used as the sensor, and so series resistance is
34
DS284PP2
CS5460A
protection is much less than 10x these values (14000 Hz and 16000 Hz), then some of the harmonic content that may be present in the voltage/current signals may start to get attenuated by this input filtering, which is undesirable. The exact values of RPV/I and CPV/I must be calculated for each particular application. The primary goal is to make sure that the input pins never receive transient input currents greater than 100 mA. Also, they should never be exposed to DC currents greater than 10 mA. The user-supplied protection resistors RPV and RPI will limit the current that comes into the pins in over-voltage situations--when the internal protection diodes turn on inside the CS5460A. For example, suppose that the value for RPI (on the current channel input) was chosen to be 1000 Ohms. Then we know that the current channel can withstand brief voltage spikes of up to ~100 V (referenced to GND) without damage to the part. This is because 100 V / 1000 Ohm = 100 mA. The pin will also be protected for up to ~10 VDC, as we see that 10V / 1000 Ohm = 10 mA. When computing appropriate values for RPV/I, the differential input impedance of the CS5460A's voltage channel and current channel should also be considered. This is especially true for the current channel, which has a lower differential input impedance than the voltage channel. These impedance specs are given at the beginning of this data sheet (see the specification titled "Effective Input Impedance" for the voltage and current channels). For example, the differential input impedance in the current channel is spec'd to be 30 kOhm. As the user increases the value of RPI to provide for more and more common-mode surge protection, the voltage drop across the external protection resistor increases, and it divides the input signal down more and more. This in turn reduces the dynamic range of the signals that are ultimately presented to the CS5460A's inputs. This voltage division by the protection resistors can sometimes by minimized, or even totally avoided: When possible, the user should first consider the input protection that is going to be necessary, and then determine the sensor gains such that the drop across the protection resistors is taken into account. Typical values for these components are RPI = 500 Ohm, CPI = 0.02 uF, CPV = 0.002 uF and if necessary, RPV = 5 kOhm.
4.14 PCB Layout
The CS5460A should be placed entirely over an analog ground plane with both the VA- and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
Note: See the CDB5460 data sheet for suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.
DS284PP2
35
CS5460A
5. REGISTER DESCRIPTION
Current Channel Voltage Channel DC Offset Register (1 x 24) AC/DC Gain Register (1 x 24)
AC Offset Register
Signed Output Registers (4 x 24) (I, V, P, E)
AC Offset Register
DC Offset Register (1 x 24)
AC/DC Gain Register (1 x 24) Unsigned Output Registers (2 x 24) (I RMS V RMS) ,
Power Offset Register
Pulse-Rate Register (1 x 24)
Cycle-Counter Register (1 x 24) Receive Buffer 24-Bit Serial Interface
Transmit Buffer
SDI CS
SDO
Control Register
Timebase Register (1 x 24)
Status Register (1 x 24)
Configuration Register (1 x 24)
Mask Register (1 x 24)
Command Word State Machine
SCLK INT
Figure 20. CS5460A Register Diagram
Note:
1.
** "default" => bit status after software or hardware reset
2. Note that all registers can be read from, and written to.
5.1 Configuration Register
Address: 0
23 PC6 15 EWA 7 RS 22 PC5 14 PH1 6 VHPF 21 PC4 13 PH0 5 IHPF 20 PC3 12 SI1 4 iCPU 19 PC2 11 SI0 3 K3 18 PC1 10 EOD 2 K2 17 PC0 9 DL1 1 K1 16 Gi 8 DL0 0 K0
Default** = 0x000001 K[3:0] Clock divider. A 4 bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of "0000" will set K to 16 (not zero). Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when CPUCLK is driving rising edge logic Control the use of the High Pass Filter on the Current Channel. 0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter is enabled. Control the use of the High Pass Filter on the voltage Channel. 0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used. (default) 1 = High-pass filter enabled
iCPU
IHPF
VHPF
36
DS284PP2
CS5460A
RS DL0 DL1 EOD Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by the reset cycle. When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin. Default = '0' When EOD = 1, EOUT becomes a user defined pin. DL1 sets the value of the EOUT pin. Default = '0' Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can also be accessed using the Status Register. 0 = Normal operation of the EOUT and EDIR pins. (default) 1 = DL0 and DL1 bits control the EOUT and EDIR pins. Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt. 00 = active low level (default) 01 = active high level 10 = falling edge (INT is normally high) 11 = rising edge (INT is normally low) Set the phase of the EOUT and EDIR output pin pulse. The EOUT and EDIR pins, on different phases, can be wire-ANDed together as a simple way of summing the frequency of different parts. 00 = phase 0 (default) 01 = phase 1 10 = phase 2 11 = phase 3 Note: EWA The above pulse-phase settings for multi-phase metering are intended for use in Normal Mode only, NOT intended for use in Stepper Mode and Mechanical Counter Mode.
SI[1:0]
PH[1:0]
Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, using an external pull-up device. 0 = normal outputs (default) 1 = only the pull-down device of the EOUT and EDIR pins are active Sets the gain of the current PGA 0 = gain is 10 (default) 1 = gain is 50 Phase compensation. A 2's complement number used to set the delay in the voltage channel. When MCLK=4.096 MHz and K=1, the phase adjustment range is about -2.8 to +2.8 degrees and each step is about 0.04 degrees (this assumes that the power line frequency is 60 Hz). If (MCLK / K) is not 4.096 MHz, the values for the range and step size should be scaled by the factor 4.096MHz / (MCLK / K). Default setting is 0000000 = 0.0215 degrees phase delay (when MCLK = 4.096 MHz).
Gi
PC[6:0]
DS284PP2
37
CS5460A
5.2 DC Current Offset Register and DC Voltage Offset Register
Address: 1 (DC Current Offset Register) 3 (DC Voltage Offset Register)
LSB 2
-1
MSB -(2 )
0
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2-17
2
-18
2
-19
2
-20
2
-21
2
-22
2-23
Default** = 0.000 The DC Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one computation cycle with the current or voltage offset when the proper input is applied and the DC Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range full scale. The numeric format of this register is two's complement notation.
5.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register
Address: 2 (Current Gain Register) 4 (Voltage Gain Register)
LSB 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22
MSB 21
Default** = 1.000 The Gain Registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The Gain Registers hold the result of either the AC or DC gain calibrations, whichever was most recently performed. If DC calibration is performed, the register is loaded after one computation cycle with the system gain when the proper DC input is applied and the Calibration Command is received. If AC calibration is performed, then after ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register) the register(s) is loaded with the system gain when the proper AC input is applied and the Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0.0 Gain < 4.0.
5.4 Cycle Count Register
Address: 5
MSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 LSB 20
Default** = 4000 The Cycle Count Register determines the length of an energy and RMS conversion. A conversion cycle is derived from (MCLK/K)/(1024N) where MCLK is master clock, K is clock divider, and N is cycle count. N must be greater than 10 for IRMS, VRMS and energy calculations to be performed.
38
DS284PP2
CS5460A
5.5 Pulse-Rate Register
Address: 6
MSB 2
18
LSB 2
17
2
16
2
15
2
14
2
13
2
12
2
11
.....
21
2
0
2
-1
2
-2
2
-3
2
-4
2-5
Default** = 32000.00Hz The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a predetermined magnitude of energy. The register's smallest valid value is 2 -4 but can be in 2-5 increments.
5.6 I,V,P,E Signed Output Register Results
Address: 7 - 10
MSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
The Signed Registers contain the last value of the measured results of I, V, P, and E. The results are in the range of -1.0 I, V, P, E < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain signed values. Note that the I, V, and P registers are updated every conversion cycle, while the E register is only updated after each computation cycle. The numeric format of this register is two's complement notation.
5.7 IRMS, VRMS Unsigned Output Register Results
Address: 11,12
MSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 LSB 2-24
The Unsigned Registers contain the last value of the calculated results of I RMS and VRMS. The results are in the range of 0.0 IRMS,VRMS < 1.0. The value is represented in binary notation, with the binary point place to the left of the MSB. IRMS and VRMS are output result registers which contain unsigned values.
5.8 Timebase Calibration Register
Address: 13
MSB 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 LSB 2-23
Default** = 1.000 The Timebase Register is initialized to 1.0 on reset, allowing the device to function and perform computations. The register is user loaded with the clock frequency error to compensate for a gain error caused by the crystal/oscillator tolerance. The value is in the range 0.0 TBC < 2.0.
DS284PP2
39
CS5460A
5.9 Power Offset Register
Address:
MSB -(2 )
0
14
LSB
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2-17
2
-18
2
-19
2
-20
2
-21
2
-22
2-23
Default** = 0.000 This offset value is added to each power value that is computed for each voltage/current sample pair before being accumulated in the energy register. The numeric format of this register is two's complement notation. This register can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system.
5.10 AC Current Offset Register and AC Voltage Offset Register
Address: 16 (AC Current Offset Register) 17 (AC Voltage Offset Register)
LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24
MSB 2-1
Default** = 0.000 The AC Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements. First, the ground-level input should be applied to the inputs. Then the AC Offset Calibration Command is should be sent to the CS5460A. After ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register), the gain register(s) is loaded with the square of the system AC offset value. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. Note that this register value represents the square of the AC current/voltage offset.
5.11 Status Register and Mask Register
Address:
15 (Status Register) 26 (Mask Register)
22 EOUT 14 IROR 6 ID0 21 EDIR 13 VROR 5 WDT 20 CRDY 12 EOR 4 VOD 19 MATH 11 EOOR 3 IOD 18 Res 10 Res 2 LSD 17 IOR 9 ID3 1 0 16 VOR 8 ID2 0 IC
23 DRDY 15 PWOR 7 ID1
Default** = 0x000000 (Status Register) 0x000000 (Mask Register) The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user can simply write back to the Status Register to clear the bits that have been seen, without concern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt, the status bit will still be set in the Status Register so the user can poll the status. The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the mask register will allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active. 40 DS284PP2
CS5460A
IC Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command. Can be deactivated only by sending a port initialization sequence to the serial port. When writing to Status Register this bit is ignored. Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (with respect to VA- pin). For a given part, this threshold can anywhere between 2.3 V to 2.7 V. Modulator oscillation detect on the current channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel's Differential Input Voltage Range. Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel's Differential Input Voltage Range. Note: This IOD and VOD bits may be `falsely' triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times.
LSD
IOD
VOD
WDT
Watch-Dog Timer. Set when there has been no reading of the Energy register for more than 5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy register, then write to the Status Register with this bit set to logic '1'. When MCLK / K is not 4.096 MHz, the time duration is 5 * [4.096 MHz / (MCLK / K)] seconds. Revision/Version Identification. /EOUT Energy Summation Register went out of range. Note that the /EOUT Energy Summing Register is different than the Energy Register available through the serial port. This register cannot be read by the user. Assertion of the this bit can be caused by having an output rate that is too small for the power being measured. The problem can be corrected by specifying a higher frequency in the Pulse-Rate Register. Energy Out of Range. Set when the calibrated energy value is too large or too small to fit in the Energy Register, which can be read via the serial port. RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the RMS-Voltage Register. RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the RMS-Current Register. Power Calculation Out of Range. Set when the magnitude of the calculated power is too large to fit in the Instantaneous Power Register. Voltage Out of Range. Current Out of Range. Set when the magnitude of the calibrated current value is too large or too small to fit in the Instantaneous Current Register. General computation Indicates that a divide operation overflowed. This can happen normally in the course of computation. If this bit is asserted but no other bits are asserted, then there is no error, and this bit should be ignored.
ID3:0 EOOR
EOR VROR IROR PWOR VOR IOR MATH
DS284PP2
41
CS5460A
CRDY EDIR EOUT Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate, which is usually 4 kHz. Set whenever the EOUT bit asserted (see below) as long as the energy result is negative. Indicates that the energy limit has been reached for the /EOUT Energy Summation Register, and so this register will be cleared, and one pulse will be generated on the /EOUT pin (if enabled). The energy flow may indicate negative energy or positive energy. This must be determined by looking at the EDIR bit (above). This EOUT bit is cleared automatically when the energy rate drops below the level that produces a 4 KHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This status bit is set with a maximum frequency of 4 KHz (when MCLK/K is 4.096 MHz). When MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate that one would expect to get with MCLK/K = 4.096 MHz by a factor of 4.096 MHz / (MCLK/K) to get the actual pulse-rate. Data Ready. When running in single or continuous conversion mode, this bit will indicate the end of computation cycles. When running calibrations, this bit indicates that the calibration sequence has completed, and the results have been stored in the offset or gain registers.
DRDY
5.12 Control Register
Address: 28
23 Res 15 Res 7 Res 22 Res 14 Res 6 MECH 21 Res 13 Res 5 Res 20 Res 12 Res 4 INTL 19 Res 11 Res 3 SYNC 18 Res 10 Res 2 NOCPU 17 Res 9 Res 1 NOOSC 16 Res 8 STOP 0 STEP
Default** = 0x000000 STOP Res MECH INTL SYNC NOCPU NOOSC STEP 1 = used to terminate the new EEBOOT sequence. Reserved. These bits must be set to zero. 1 = widens EOUT and EDIR pulses for mechanical counters. 1 = converts the /INT output to open drain configuration. 1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command. 1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption. 1 = saves power by disabling the crystal oscillator for external drive. 1 = enables stepper-motor signals on the EOUT/EDIR pins.
42
DS284PP2
CS5460A
6. PIN DESCRIPTION
Crystal Out CPU Clock Output Positive Digital Supply Digital Ground Serial Clock Input Serial Data Output Chip Select Mode Select Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input XOUT CPUCLK VD+ DGND SCLK SDO CS MODE VIN+ VINVREFOUT VREFIN
1 2 3
4
24 23 22
21
XIN SDI EDIR EOUT INT RESET NC PFMON IIN+ IINVA+ VA-
Crystal In Serial Data Input Energy Direction Indicator Energy Output Interrupt Reset No Connect Power Fail Monitor Differential Current Input Differential Current Input Positive Analog Supply Analog Ground
5 6
7
20 19
18
8 9 10 11 12
17 16 15 14 13
Clock Generator
Crystal Out Crystal In CPU Clock Output Serial Clock Input
1,24 XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. Alternatively, an external (CMOS compatible clock) can be supplied into XIN pin to provide the system clock for the device. CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
2
Control Pins and Serial Data I/O
5 SCLK - A clock signal on this pin determines the input and output rate of the data for the SDI and SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. SDO - SDO is the output pin of the serial data port. Its output will be in a high impedance state when CS is high. CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO pin to a high impedance state. CS should be changed when SCLK is low. MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the aid of an external serial EEPROM to receive commands and settings. When at logic low, the CS5460A assumes normal command-mode operation. This pin is pulled down to logic low if left unconnected. INT - When INT goes low it signals that an enabled event has occurred. INT is cleared (logic 1) by writing the appropriate command to the CS5460A. EOUT - The energy output pin output a fixed-width pulse rate output with a rate (programmable) proportional to energy. EDIR - The energy direction indicator indicates if the measured energy is negative. SDI - the input pin of the serial data port. Data will be input at a rate determined by SCLK.
Serial Data Output Chip Select Mode Select
6 7 8
Interrupt Energy Output Energy Direction Indicator Serial Data Input Differential Voltage Inputs
20 21 22 23
Measurement and Reference Input
9,10 VIN+, VIN- - Differential analog input pins for voltage channel.
DS284PP2
43
CS5460A
Voltage Reference Output Voltage Reference Input Differential Current Inputs Positive Digital Supply Digital Ground Negative Analog Supply Positive Analog Supply Power Fail Monitor
11 12 15,16 VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 2.5 V and is reference to the VA- pin on the converter. VREFIN - The voltage input to this pin establishes the voltage reference for the on-chip modulator. IIN+, IIN- - Differential analog input pins for current channel.
Power Supply Connections
3 4 13 14 17 VD+ - The positive digital supply is nominally +5 V 10% relative to DGND. DGND - The digital ground is at the same level as VA-. VA- - The negative analog supply pin must be at the lowest potential. VA+ - The positive analog supply is nominally +5 V 10% relative to VA-. PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level is 2.5 V with respect to the VA- pin, with +/-50 mV of hysteresis. If PFMON voltage threshold is tripped, the LSD (low-supply detect) bit is set in the Status Register. Reset - When reset is taken low, all internal registers are set to their default states.
RESET
19
18
Other
No Connection NC - No connection. Pin should be left floating.
44
DS284PP2
CS5460A
7. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4
MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4
NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150
Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS284PP2
45
CS5460A
24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
DIM A A1 b C D E e H L
MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0
INCHES NOM 0.098 0.008 0.017 0.011 0.606 0.295 0.050 0.407 0.026 4
MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8
MIN 2.35 0.10 0.33 0.23 15.20 7.40 1.02 10.00 0.40 0
MILLIMETERS NOM 2.50 0.20 0.42 0.28 15.39 7.50 1.27 10.34 0.65 4
MAX 2.65 0.30 0.51 0.32 15.60 7.60 1.52 10.65 1.27 8
JEDEC #: MS-013
Controlling Dimension is Millimeters
46
DS284PP2
* Notes *

▲Up To Search▲

Price & Availability of CS5460A-KS

	To Download CS5460A-KS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .